The concept of “Interrupt” is purely based on common-sense. To give you an example, imagine a parallel port in your PC being connected to a printer. During a print operation in progress, the CPU supplies characters to the parallel port (to be passed onto the printer) at a periodic rate. Say, the parallel port runs out of data after printing 1000 characters. Now the parallel port starts to “starve” for more characters. The processors job is to identify the hungry parallel port and feed it with more characters. Here comes the concept of “interrupt”.
“Interrupt” is a signal used by an I/O device (like a parallel port) to inform the CPU that it has to feed the parallel port with more characters. As soon as the interrupt signal (an output of the I/O device) is received, the processor devotes it’s attention towards the corresponding I/O device. In the above example, the CPU then does a “write” operation to the parallel port.
Similarly, an interrupt could be signalled by an I/O device (say a floppy disk-controller) indicating that it is completely filled with data and hence the CPU may initiate a “read” operation, to retrieve the data.
Usually, the microprocessors have only one input request line. Hence it is not possible to connect all the interrupt request lines from various I/O devices directly to this single input. They are rather connected to a device called interrupt controller.
How does the interrupt-signaling process occur?
The figure below depicts the steps involved in an interrupt-signaling process:
The interrupt controller samples all the request lines coming into it, from various I/O devices. Let us assume that the total # of request lines is 8 (as shown in fig 1). All the 8 requests cannot be serviced at the same time. Hence the requests are serviced based on a pre-determined priority scheme. Typically, the highest-priority request is serviced first, followed by the next-highest priority request. The 8 requests are registered (stored) in a register called Interrupt Request Register (IRR).
As soon as the CPU samples an activity on the INTR input signal, it wants to know the identity of the I/O device that caused the interrupt. For this, the CPU generates 2 back-to-back Interrupt acknowledge bus cycles. In other words, the CPU sends a signal called INTA (interrupt acknowledge) in the form of 2 pulses, to the interrupt controller.
As soon as the interrupt controller samples an activity on the INTA signal (i/p to the interrupt ctlr), it responds as follows
Response to pulse 1 of INTA:
as soon as the first pulse of the INTA signal is sampled, the highest priority bit of the Interrupt Service register (ISR) is reset. This is just to indicate that the particular interrupt that the CPU intends to service will no longer be of highest-priority. (The next-highest priority interupt will now become highest-priority”).
But since the service of the highest priority interrupt has not been completely done, the interrupt controller still needs to remember this request of highest priority, somehow. Hence the first pulse of INTA is used to update a register called Interrupt Service Register (ISR).
Response to pulse 2 of INTA:
as soon as the rising edge of the second pulse of the INTA signal is sampled, the interrupt controller creates an 8-bit number, called an Interrupt vector. Each I/O device has a separate interrupt-vector allotted by the interrupt controller. The interrupt-vector is output to the CPU.
The CPU samples the interrupt-vector at the falling edge of the second INTA pulse. The interrupt-vector points to a specific address location in a table called interrupt-table. The data stored in these address locations is again another adrress where the interrupt service routine is stored.
Note: Interrupt service routine is nothing but a program that has instructions as to how the interrupt has to be serviced.
After the CPU completes servicing the interrupt, it resumes the same operation that it was doing, before the interrupted occured. For this, the CPU’s Code segment (CS) and Instruction Pointer (IP) registers point to the location in the memory where the suspended instruction has to be fetched.